The present invention relates to a semiconductor device such as a lateral double diffusion MOS transistor or the like that needs a high breakdown voltage and low power consumption, and a manufacturing method thereof.
In a conventional lateral double diffusion MOS (Metal Oxide Semiconductor) transistor (called “LDMOS”), an N-type LDMOS is formed which includes a local insulating layer comprised of silicon oxide, which is formed in an N well layer formed by diffusing an N-type impurity into a P-type semiconductor substrate in a low concentration, a drain layer formed by diffusing an N-type impurity into the N well layer lying in a region adjacent to one side of the local insulating layer in a high concentration, a P body diffusion layer formed by diffusing a P-type impurity into the N well layer lying in a region separated from the other side of the local insulating layer in a low concentration, a source layer formed by diffusing an N-type impurity into the P body diffusion layer in a high concentration, a gate electrode formed over the N well layer lying in a region extending from over the local insulating layer to the source layer, a first gate insulating film formed between the gate electrode and the N well layer, and a second gate insulating film, which is formed in a region adjacent to the other side of the local insulating layer and which is connected to the first gate insulating film and thicker than the first gate insulating film and thinner than the local insulating layer. An end on the source layer side, of the second gate insulating film thick in thickness is caused to approach the P body diffusion layer in a range in which they do not overlap, and the length of a drift drain region is substantially increased by the local insulating layer formed in the N well layer, thereby enhancing a source-to-drain breakdown voltage (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2007-67181 (mainly paragraph 0019 in page 6—paragraph 0047 in page 8 and FIGS. 3A and 4)).
With a body diffusion layer formed below the source layer and a semiconductor layer provided therearound as different conductivity-type diffusion layers, such an LDMOS enhances a source-to-drain breakdown voltage at an OFF state of the gate electrode by a depletion layer which expands the semiconductor layer from a PN junction formed in the boundary therebetween to the drain layer. There has however been proposed an LDMOS (called “resurf LDMOS”) wherein in order to further enhance the source-to-drain breakdown voltage, a conductivity-type drift diffusion layer different from the semiconductor layer is formed below the drain layer, and the PN junction formed in the boundary to the semiconductor layer lying therearound, and the drain layer are caused to approach therebetween thereby to facilitate the formation of a depletion layer that expands the drift diffusion layer from the PN junction to the drain layer, thus making it possible to enhance a source-to-drain breakdown voltage (refer to, for example, a non-patent document 1 (Y. Kawagutchi et al., ┌0.6 μm BiCMOS Based 15 and 25V LDMOS for an Analog Application┘, Proc. 2001 int. Symp. Power Semiconductor Devices & ICs, p. 169)).
The above-described resurf LDMOS has an advantage in that when the differences in concentration for forming the PN junctions between the resurf LDMOS and the LDMOS described in the patent document 1 are made identical, the source-to-drain breakdown voltage (hereinafter called simply “breakdown voltage”) at the OFF state of the gate electrode can be brought to a higher breakdown voltage as compared with the LDMOS described in the patent document 1. If this advantage is utilized, then the diffusion concentration of the drift diffusion layer is set to a higher concentration in the case of the same breakdown voltage to more reduce an ON resistance, thereby making it possible to attain a further reduction in power consumption. The present situation is however that a practicable resurf LDMOS has not been realized.
This is because when the gate insulating film lying below the gate electrode is set to a normal thickness for operating the resurf LDMOS, the concentration of an electric field becomes easier to occur directly below the end on the source layer side, of the local insulating layer in the drift diffusion layer, and obtaining a predetermined ON resistance at a predetermined breakdown voltage becomes difficult.